CV

Software Engineer

Lockheed Martin Skunkworks/ADP

Supported IRAD and other efforts with both design and ground/flight test support activities.

• Wrote SystemVerilog FPGA code for Xilinx MPSoC FPGAs in avionics systems, and Tcl scripts for automation.
• Documented lab equipment assembly and generated drawings using Catia V5 and Solidworks.
• Managed lab hardware procurement and inventory, up to $1.2 mil annually. Dealt directly with vendors.
• Supported testbed operations (flight test, truck test) including building and troubleshooting test setups.

Firmware Engineer III

Kratos Defense and Security Solutions, Inc.

Worked as an FPGA firmware engineer in support of DSP efforts.

• Developed FPGA firmware for Xilinx MPSoCs, tested with software (Python, C++) scripts on no-OS and PetaLinux builds. Debugged firmware using Vitis and JTAG connections as well as using software scripts on the board’s processor (for MPSoCs).
• Implemented and tested C++/Python software and FPGA firmware on ICE FPGA cards using NeXT Midas.

Software Engineer Sr

Lockheed Martin Space

Current role, working as an FPGA design engineer supporting a software simulation group.

• Designed and simulated FPGA firmware using SystemVerilog and VHDL. Simulated using UVM and self-checking test benches. Wrote software test scripts and documentation as part of integration.
• Acted as lead for R&D efforts. Coordinated progress, schedule, and equipment cost with stakeholders and managers.
• Designed circuitry using Cadence OrCAD and simulated in PSPICE to verify functionality. Prototyped and tested circuits by both breadboarding and soldering components onto protoboards.
• Implemented a low-footprint Microk8s experiment (using Python) onto the LINUSS satellite to demonstrate functionality in a hardware-constrained environment. Automated deployment using YAML and bash scripts.
• Technical POC/Functional Owner of RTOS lab test environment, responsible for hardware and software configuration as well as cybersecurity (STIG) compliance. Acted as property coordinator for lab team.
• Lab hardware support, including wire harness design and hardware debugging/deployment.

MS

Johns Hopkins University

Electrical Engineering

• Digital Signal Processing
• System-on-a-Chip FPGA Design Laboratory
• FPGA Design Using VHDL
• Machine Learning for Signal Processing
• Embedded Systems Development Lab
• Computer Architecture
• UAV Systems and Control
• Probability and Stocastic Processes for Engineers
• UAV Systems and Control
• Masters Thesis

BS

California State University Northridge

Electrical Engineering

• Computing for Electrical Engineers
• Digital Design with Verilog and SystemVerilog
• FPGA Design Using VHDL
• FPGA/ASIC Design and Optimization Using VHDL
• Fundamental Control Systems
• Introduction to Solid State Devices
• Linear Systems I
• Linear Systems II
• Digital Electronics
• Digital System Design with Programmable Logic
• Electrical Engineering Fundamentals
• Electromagnetic Fields and Waves
• Electronics I
• Electronics II
• Engineering Economics and Analysis
• Engineering Materials
• Mathematical Models in EE
• Num. Methods in Engineering
• Probabilistic Systems in EE Design and Analysis
• Theory of Digital Systems
• Thermodynamics

Resource and Performance Improvements of Optimized Convolutional Neural Networks for FPGA Implementations of Automatic Modulation Recognition

2025 59th Annual Conference on Information Sciences and Systems (CISS), 2025

Abstract: Automatic Modulation Recognition (AMR), commonly found in software defined radios, relies on speed and accuracy to effectively interpret the modulation type of incoming signals. Convolutional Neural Networks (CNNs) are growing in popularity over traditional algorithms due to their excellent performance with classification-type problems – but these are typically resource intensive, and Radio Frequency (RF) receivers are typically part of a larger system that can benefit from less resources being tied to this classification task. Field Programmable Gate Array (FPGA) implementations provide better performance than CPU and GPU implementations in most cases, and the added benefit of these functions being off the processor allows the entire system to perform better. Since resource utilization is such a critical component of effective CNN implementation, and it is often inversely tied to performance, the effectiveness of various hardware optimization techniques as well as their effects on performance should be considered by the designer. This work evaluates the tradeoffs of various model optimizations and how they affect both implementation and performance, synthesizing the models using Xilinx’s quantization-aware FINN library. In this work, a methodology is presented for the generation of I and Q signals for CNN model training and evaluation, and the performance and hardware utilization benchmarks are evaluated to determine both design considerations and effective approaches for optimizing these models for real-world implementation.

Quantization and Pruning of Convolutional Neural Networks for Efficient FPGA Implementation of Digital Modulation Detection Firmware

Johns Hopkins University

Abstract: Automatic modulation detection is an important function of communications systems. Commonly found in software defined radios, it enables radio receivers to interpret multiple and potentially changing modulation types without needing manual input from the user. Due to vastly increasing performance, many modern systems are moving away from the traditional two-stage process of feature extraction and classification; instead, a neural-network based system (also known as deep learning) is being utilized with increased speed and virtually no loss in accuracy. These implementations, when placed on hardware or on a Field Programmable Gate Array (FPGA), provide the fastest performance; but until recently the barrier of entry has been the size of the neural networks and the infeasible amount of resources they would need to occupy on the FPGA fabric. This thesis explores the effects of both quantization and pruning on convolutional neural network models of various sizes while maintaining high classification accuracy for the digitally modulated signals generated. In this thesis, a framework is proposed for the generation of the signals, models, and hardware estimation to serve as a guide for efficient deep learning implementations of models intended to fit on hardware with limited resources. The results demonstrate tradeoffs and design considerations that balance performance and implementation size for engineers aiming to implement a deep learning-based automatic modulation detection scheme on FPGAs.

OpenCV Facial Recognition Lock

System with SMS alerts and server logging for unauthorized entry attempts.

• OpenCV
• Python

Implementing DDR2 Cache Memory

Implementing DDR2 Cache Memory using the Xilinx Memory Interface Generator on a pipelined MIPS processor.

• Xilinx Vivado
• Memory Interface Generator
• DDR2

Detecting COVID-19 from Chest X-Rays

Using machine learning algorithms to detect COVID-19 and other respiratory illness using radiographic images.

• Matlab
• Machine Learning